1. Field of the Invention
The present invention relates to a multilayer chip varistor and a method of manufacturing the same.
2. Related Background Art
There is a known multilayer chip varistor including a varistor body obtained by sintering a stack of varistor layers and inner electrode, and terminal electrodes formed by applying conductive paste on end faces of the varistor body and thereafter drying and baking the applied paste.
The conductive paste that is frequently used for forming the terminal electrodes is obtained by mixing glass frit and organic vehicle with metal powder, a principal constituent, such as silver. The glass frit is mixed into the conductive paste for the purpose of improving adhesion properties of the varistor body and the terminal electrodes.
This type of multilayer chip varistor is mounted on a printed circuit board and the like typically in a method of so-called reflows soldering. In this method, the varistor is put on solder paste which has been applied to a conductor on the board in advance, and thereafter, the entire board is heated to a temperature of 200 degrees centigrade or higher to melt the solder so that the varistor is fixed to the board.
At this time, it is often the case where the terminal electrodes are plated with nickel and then further plated with solder, tin or the like in order to improve wettability of the terminal electrode to the solder during reflow soldering.
However, when the terminal electrodes are plated, a plating solution enters inside of the varistor body, and the plating solution which entered inside of the varistor body sometimes corrodes the varistor layers in the varistor body, in particular, a grain boundary of a varistor material that constructs the varistor layers. Since varistor characteristics of the multilayer chip varistor is considered to be effective at the grain boundary, this corrosion of the grain boundary causes a degradation of the varistor characteristics of the multilayer chip varistor such as a decrease in varistor voltage and the like. Such degradation of the varistor characteristics may be observed immediately after plating or after the varistor is mounted on the board by reflow soldering.
In order to prevent the degradation of the varistor characteristics due to entry of a plating solution, various measures have been taken in recent multilayer chip varistors. For example, multilayer chip varistors described in Japanese Patent Laid-Open Publication No. Heisei 8-31616 and Japanese Patent Laid-Open Publication No. Heisei 10-70012 are known. FIG. 6 is a cross sectional view showing a multilayer chip varistor same as those described in the above-mentioned publications. The multilayer chip varistor shown in FIG. 6 has a varistor body 10 having inner electrodes 11 and terminal electrodes 12 provided on ends of the varistor body 10. In addition, insulating protection layers 13 are formed in portions of the varistor body 10, where the terminal electrodes 12 are not formed. In this multilayer chip varistor, the insulating protection layers 13 play a role of preventing the plating solution entering inside the varistor body 10.
Further, a multilayer chip varistor described in Japanese Patent Laid-Open Publication No. 2000-164406 is also known as the one in which entry of a plating solution into the varistor body can be reduced. FIG. 7 is a cross sectional view showing the multilayer chip varistor described in the above-mentioned publication. The multilayer chip varistor shown in FIG. 7 includes a varistor body 10 having inner electrodes 11 and ground electrode layers 14 provided on the ends of the varistor body 10. In addition, a glass layer 15 and external electrode layers 16 are formed on the outer sides of the ground electrode layers 14. Further, a conductive material is diffused within the glass layer 15, and thereby continuity between the ground electrode layers 14 and the external electrode layers 16 is realized.
Furthermore, a multilayer chip varistor is described in Japanese Patent Laid-Open Publication No. 2002-134306, in which terminal electrodes are formed using conductive paste containing a predetermined amount of conductive glass frit or a larger amount of the same. In this multilayer chip varistor, a content of the glass frit within the terminal electrodes is larger than that in a conventional varistor to reduce voids in the terminal electrodes, preventing a plating solution from penetrating the terminal electrodes. In addition, the use of conductive glass frit containing tin oxide or antimony oxide prevents a reduction in wettability to solder which often occurs as the amount of glass frit increases.
Furthermore, conductive paste containing glass frit having a particular composition is described in Japanese Patent Laid-Open Publication No. Heisei 6-349313 and Japanese Patent Laid-Open Publication No. 2001-122639. Terminal electrodes of a multilayer type element formed by this conductive paste is excellent in resistance to a plating solution, and it is thus proved that these terminal electrodes can prevent degradation of characteristics of the element due to entry of the plating solution.